CVE-2024-24853

CVSS 7.3 HIGHEPSS 0.2%CWE-696

Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.

CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/VI:H/VA:H/SC:H/SI:H/SA:H

Produtos afetados

n/a · Intel(R) Processor

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Referências

https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01083.html